library ieee;
use ieee.std_logic_1164.all;




entity im is port (
 
ing: in std_logic_vector(31 downto 0);
uscita: out std_logic_vector




); end entity;



architecture bim of im is 


type mem is array(128 to 0) of std_logic_vector(31 downto 0);


begin 





uscita <="0000000000000000";





end architecture;


